Title :
Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design
Author :
Indermaur, T. ; Horowitz, M.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
A technique called charge recovery or adiabatic switching has been proposed to trade speed for energy consumption in CMOS circuits. We compare the speed/power of charge recovery to standard CMOS logic operating at different supply voltages and demonstrate that the overhead of charge recovery limits the overall power savings. In almost all cases, voltage scaled CMOS dissipates less power for the same level of performance.
Keywords :
CMOS logic circuits; CMOS logic; adiabatic switching; charge recovery circuits; energy consumption; low power CMOS design; voltage scaled CMOS; Analytical models; Delay; Energy consumption; Inductors; Power dissipation; Rails; Semiconductor device modeling; Switches; Switching circuits; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573221
