Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences

A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delay-lock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 mum complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.