Analytical derivation of power semiconductor losses in MOSFET multilevel inverters

Multilevel topologies reduce the required filter effort and therefore the weight and volume of the system. Additionally some topologies have a built in redundance and increase the reliability. The cooling of the power semiconductors and thus the power dissipation is a crucial criterion for the design of a PWM converter. Methods for the calculation of power semiconductor losses in two level inverters and in some three level inverter topologies are well known. Here a complete analytical calculation of power semiconductor losses for different five level inverter topologies is presented. Conduction losses as well as switching losses are included in the calculations. These are based on the power semiconductor datasheet information using a simplified model. The derived equations are applied to the different topologies and the results are compared to each other.