Testing transition delay faults in modified Booth multipliers by using C-testable and SIC patterns

In this paper, we design a novel modified Booth multiplier and generate test patterns for transition delay faults (TDF) at cell-level and gate-level descriptions of the multipliers. Regular structures of these multipliers make single stuck-at faults (SAF) at both description levels be C-testable. Single TDF of the multipliers are also detectable with constant test pairs since the second vector for a TDF is also a test pattern of a SAF at the same faulty site. We generate these required constant test pairs, which are fewer than those obtained by commercial tools. These test pairs can also detect all SAF at both description levels. In addition, a TDF within a cell behaves sequentially at the cell´s I/O, which is very similar to the definition of RS-CFM (realistic sequential cell fault model). Consequently, we also generate required SIC (single input change) test pairs for RS-CFM and verify their efficiency on testing RS-CFM and TDF. The number of searched SIC test pairs is linear with respect to multiplier sizes, just like those provided by a previous work. Nevertheless, comparing with that work, we can generate very few SIC test pairs to achieve similarly high fault coverage for RS-CFM.