Title :
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing
Author :
Enokimoto, K. ; Wen, X. ; Yamato, Y. ; Miyase, K. ; Sone, H. ; Kajihara, S. ; Aso, M. ; Furukawa, H.
Author_Institution :
Kyushu Inst. of Technol., Fukuoka, Japan
Abstract :
Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.
Keywords :
automatic test pattern generation; boundary scan testing; integrated circuit testing; CAT scheme; X-filling; at-speed scan testing; critical-area-targeted test set modification scheme; integrated circuits testing; launch switching activity reduction; launch-safety checking; test relaxation; test-induced yield loss; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Crosstalk; Delay; Lab-on-a-chip; Logic testing; Safety; System testing; Clock-Gating; Power Supply Noise; Test Relaxation; X-Filling;
Conference_Titel :
Asian Test Symposium, 2009. ATS '09.
Conference_Location :
Taichung
Print_ISBN :
978-0-7695-3864-8
DOI :
10.1109/ATS.2009.22