DocumentCode
2755589
Title
A Practical DFT Approach for Complex Low Power Designs
Author
Kifli, Augusli ; Chen, Y.W. ; Tsay, Y.W. ; Wu, K.C.
Author_Institution
Faraday Technol. Corp., Hsinchu, Taiwan
fYear
2009
fDate
23-26 Nov. 2009
Firstpage
90
Lastpage
91
Abstract
Low power designs create new challenges in design implementation, verification and testing. DFT practice that overlooks test power may result in yield loss/overkill during manufacturing test. This paper addresses the practical problems often encountered during DFT implementation and manufacturing test for complex low power designs.
Keywords
design for testability; low-power electronics; production testing; DFT; complex low power design; design for testability; design implementation; design testing; design verification; manufacturing test; test power problem; yield loss; Automatic test pattern generation; Circuit testing; Consumer electronics; Design for testability; Dynamic voltage scaling; Energy consumption; Job shop scheduling; Logic testing; Pulp manufacturing; Switches; ATPG; DFT; MSMV; low-power;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2009. ATS '09.
Conference_Location
Taichung
ISSN
1081-7735
Print_ISBN
978-0-7695-3864-8
Type
conf
DOI
10.1109/ATS.2009.61
Filename
5359399
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