DocumentCode
2755884
Title
On Scan Chain Diagnosis for Intermittent Faults
Author
Adolfsson, Dan ; Siew, Joanna ; Marinissen, Erik Jan ; Larsson, Erik
Author_Institution
NXP Semicond. Corp. Innovation & Technol., Eindhoven, Netherlands
fYear
2009
fDate
23-26 Nov. 2009
Firstpage
47
Lastpage
54
Abstract
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lower bound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.
Keywords
failure analysis; integrated circuit testing; logic circuits; logic testing; bound calculation algorithm; failing ICs analysis; high-volume test response analysis; intermittence probability; intermittent faults; scan chain defects; scan chain diagnosis; scan chain test pattern; Computer science; Digital systems; Failure analysis; Fault diagnosis; Logic testing; Marine technology; Probability; Semiconductor device testing; System testing; Technological innovation; diagnosis; integrated circuit; intermittent fault; scan chain; test;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2009. ATS '09.
Conference_Location
Taichung
ISSN
1081-7735
Print_ISBN
978-0-7695-3864-8
Type
conf
DOI
10.1109/ATS.2009.74
Filename
5359415
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