Testing in nanometer technologies

Summary form only given. The last 25 years has seen a dramatic increase in gate count and the Design for Testability techniques such as Full Scan, LSSD, BIST, etc. have been developed to cope with this. However, there is now a significant difference brought on by the technology developments facing us. The onset of deep sub-micron (now currently alluded to as Nanometer Technology) is changing the way chips are being designed and manufactured. Because of the large capacity of these new chips, plus the expense of new designs, embedded systems are setting the pace for today and the future. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality in this new design environment. Test is one part of this process that is getting significant attention. An area once classified as a “back end” process in the design flow is moving closer to the “front end”. Design methodologies are incorporating test-related structures in the beginning of the design cycle. In addition, standards to manage the test complexity of these large designs are being proposed. For example, IEEE P1500 is working towards defining a structure for embedded cores such that tests can be delivered to these cores. This alone is a strong challenge for the Test Community. It is clear that the design and testing of embedded systems is the key challenge facing the Test Community