A Random Jitter RMS Estimation Technique for BIST Applications

This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved inverter, and whose frequency difference from the OR operation and the AND operation is used in calculating the RMS value of the random jitter. Circuit-level simulations show the validity of the proposed technique for up to 20% peak-to-peak jitter in the clock even with process variations. The proposed technique can be applied to BIST solutions for random jitter measurement on a transmitted clock signal.