Title :
Automatic verification of scheduling results in high-level synthesis
Author :
Eveking, Hans ; Hinrichsen, Holger ; Ritter, Gerd
Author_Institution :
Dept. of Electr. & Comput. Eng., Darmstadt Univ. of Technol., Germany
Abstract :
A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs
Keywords :
circuit CAD; formal verification; high level synthesis; scheduling; AFAP; CAD; DLS; assimilation algorithm; automatic equivalence verification; automatic formal verification; cyclic control flows; high-level synthesis; pipelined designs; scheduling results; Automatic logic units; Design engineering; Equations; Flow graphs; Force control; Formal verification; High level synthesis; Logic circuits; Pipelines; Processor scheduling;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761097
