Title :
CRUSADE: hardware/software co-synthesis of dynamically reconfigurable heterogeneous real-time distributed embedded systems
Author_Institution :
Bell Labs., Lucent Technol., Holmdel, NJ, USA
Abstract :
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-time reconfigurable hardware components such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). In this paper, we address the problem of hardware/ software co-synthesis of dynamically reconfigurable embedded systems. Our co-synthesis system, CRUSADE, takes as an input embedded system specifications in terms periodic acyclic task graphs with rate constraints and generates dynamically reconfigurable heterogeneous distributed hardware and software architecture meeting real-time constraints while minimizing the system hardware cost. We identify the group of tasks for dynamic reconfiguration of programmable devices and synthesize an efficient programming interface for reconfiguring reprogrammable devices. Real-time systems require that the execution time for tasks mapped to reprogrammable devices are managed effectively such that real-time deadlines are not exceeded. To address this, we propose a technique to effectively manage delay in reconfigurable devices. Our approach guarantees that the real-time task deadlines are always met. To the best of our knowledge, this is the first co-synthesis algorithm which targets dynamically reconfigurable embedded systems. We also show how our co-synthesis algorithm can be easily extended to consider fault-detection and fault-tolerance. Application of CRUSADE and its fault tolerance extension, CRUSADE-FT to several real-life large examples (up to 7400 tasks) from mobile communication network base station, video distribution router, a multi-media system, and synchronous optical network (SONET) and asynchronous transfer mode (ATM) based telecom systems shows that up to 56% system cost savings can be realized
Keywords :
embedded systems; fault tolerant computing; graph theory; hardware-software codesign; programmable logic devices; reconfigurable architectures; ATM; CRUSADE; complex programmable logic devices; dynamically reconfigurable systems; execution time; fault-detection; fault-tolerance; field programmable gate arrays; hardware/software co-synthesis; heterogeneous real-time distributed embedded systems; mobile communication network base station; multi-media system; periodic acyclic task graphs; rate constraints; real-time constraints; real-time deadlines; synchronous optical network; system hardware cost; video distribution router; Asynchronous transfer mode; Costs; Dynamic programming; Embedded system; Field programmable gate arrays; Hardware; Programmable logic arrays; Programmable logic devices; Real time systems; SONET;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761103