Title :
A digital partial built-in self-test structure for a high performance automatic gain control circuit
Author :
Lechner, A. ; Ferguson, J. ; Richardson, A. ; Hermes, B.
Author_Institution :
Fac. of Appl. Sci., Lancaster Univ., UK
Abstract :
it is now widely recognised that design-for-testability and built-in self-test techniques will be mandatory to meet test and quality specifications in next generation mixed signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%
Keywords :
CMOS integrated circuits; automatic gain control; built-in self test; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; production testing; design-for-testability; digital BIST structure; digital on-chip post processing function; double metal CMOS; gain step size test; high performance AGC circuit; next generation mixed signal integrated systems; ramp test; reduced production test time; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Gain control; Hip; Identity-based encryption; Signal design; System testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761127
