Title :
Embedded core test plug-n-play: is it achievable?
Abstract :
The testing of embedded cores (or Virtual Components (VCs), as the VSI Alliance calls them) in an environment where the system-chip is composed of multiple cores from different authors, requires that the chosen test strategy and methodology allow for the identification of the failing core (VC), as well as determining that the manufactured chip is of sufficient quality to ship to a customer. This imposes several unique requirements, which are discussed. It is suggested that there are defect types which have no equivalent faults models. The only way to observe the presence of these manufactured defects is through system level functional tests, with guardbands on the power supplies and timing. Only in this manner will most of the latent defects that cause interaction problems between cores be observed and caught before delivery to customer
Keywords :
VLSI; automatic testing; built-in self test; integrated circuit testing; logic testing; standardisation; BIST; VLSI; embedded core test; faults models; interconnect test; multiple cores; plug-n-play; shadow logic test; system level functional tests; test access; test isolation; Built-in self-test; Logic design; Logic testing; Manufacturing; Marine vehicles; Master-slave; Multiplexing; System testing; Virtual colonoscopy; Wiring;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639729
