Fast, robust DC and transient fault simulation for nonlinear analogue circuits

The evaluation of analogue and mixed-signal test strategies and design for test techniques requires the fault simulation of analogue circuits. The need to reduce fault simulation time for has resulted in the research into concurrent analogue fault simulation, analogous to digital fault simulation. Concurrent simulation can reduce the simulation time by avoiding repeated construction of the circuit matrix. Fault collapsing and dropping is also desirable. A robust, fast algorithm for concurrent analogue fault simulation is presented in this paper. Three techniques for the automatic dropping of faults have been addressed: a robust closeness measurement technique; a late start rule and an early stop rule. The algorithm has been successfully applied to both DC and transient analyses. A significant increase in the speed of analogue fault simulation has been obtained