Fine pitch package mounting with TAB tape

The authors describe the basic concepts, development, assembly, and qualification testing of a ceramic leaded package for high-pin-count VLSI (>200 I/Os). The design has been aimed at achieving high-speed logic, testability, and reliability for a small pitch (<25 mil) package. To improve the electrical performance, ground and voltage distributions are separated from the logic circuitry connected by the surface mounting process. At the design level, thermal exchange and mechanical strength of the package were simulated using ANSYS thermomechanical software. Testability and availability of connections for burn-in before mounting are provided by the use of 50-mil-pitch test pads interconnected to the leads. The preferred solution for external connection and test pads is provided by the use of a TAB (tab automated bonding) lead frame bonded to the ceramic package. After burn-in and test, outer test pads are separated and the package is surface mounted. The TAB lead frame provides an optimized solution. Mounting to the printed circuit board is achieved using a thermode tool or laser soldering. Qualification results and mountability tests are satisfactory