A methodology and design environment for DSP ASIC fixed point refinement

Author

Cmar, R. ; Rijnders, L. ; Schaumont, P. ; Vernalde, S. ; Bolsens, I.

Author_Institution

IMEC, Leuven, Belgium

fYear

1999

fDate

1999

Firstpage

271

Lastpage

276

Abstract

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods

Keywords

application specific integrated circuits; circuit optimisation; digital signal processing chips; error statistics; fixed point arithmetic; floating point arithmetic; hardware description languages; hardware-software codesign; integrated circuit design; object-oriented methods; quantisation (signal); C++ object oriented description; DSP ASIC; LSB weights; MSB weights; VHDL; complex signal processing algorithms; design environment; error statistics; fast convergence; fixed point refinement; floating point precision; hardware implementation; independent strategies; quantization process; short design cycles; simulation statistics; type refinement; Analytical models; Application specific integrated circuits; Design methodology; Digital signal processing; Electrical capacitance tomography; Modems; Monitoring; Quantization; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761133

Filename

761133