An efficient metric normalization architecture for high-speed low-power viterbi decoder

In this paper, a new efficient metric normalization architecture called high bit clear is proposed for a high throughput and low power Viterbi decoder (VD). The proposed high bit clear normalization circuit not only normalizes all of the survivor path metrics, but also operates as close as the add-compare-select (ACS) iteration bound possibly with a small area overhead. After we verified the function and made the platform by FPGA, we also used United Microelectronics Corporation (UMC) 0.18 mum 1.8 V 1P6M standard cell library to implement it. With implementation by using UMC 0.18 mum 1.8-V standard cell library, the proposed VD can improve the data rate up to 834 Mbps for decoding a (3,1,2) convolutional code. To compare with the traditional VD without normalization, the proposed VD is improved by 60% in decoding speed and reduced by 50% in power consumption. Furthermore, the chip area of the new VD is reduced by 55% as compared to the traditional one. The operational speed of the proposed VD is up to 278MHz. Under 278MHz operation, the proposed VD consumes 2.48mW in power and the chip area utilized is about 110 mum*110 mum.