DocumentCode :
275677
Title :
Systolic array building blocks for real-time signal processing
Author :
Hargrave, P.J. ; Ward, C.R.
fYear :
1991
fDate :
15-19 Apr 1991
Firstpage :
24
Lastpage :
29
Abstract :
The authors describe the application of a number of contrasting module designs to adaptive processing systems. In particular, they illustrate that, whereas the transputer can effectively implement complex parallel algorithms designed for audio band problems similar algorithms for RF antenna array processing have demanded the development of a special DSP chip offering a much higher processing throughput performance. They describe a transputer implementation of an acoustic adaptive beamformer and a special Node Chip implementation of a radio frequency adaptive beamformer. The implementation of this 4-channel adaptive array module (4-ASAM) required a 2 MHz bandwidth and 300 MFLOPS of processing power
fLanguage :
English
Publisher :
iet
Conference_Titel :
Design and Application of Parallel Digital Processors, 1991., Second International Specialist Seminar on the
Conference_Location :
Lisbon
Print_ISBN :
0-85296-519-2
Type :
conf
Filename :
140012
Link To Document :
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