Analysis and optimization of series-gated CML bipolar circuits

Author

Sharaf, Khaled ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

2

fYear

1994

fDate

3-5 Aug 1994

Firstpage

1133

Abstract

An analytical model for calculating propagation delay time of two-level series-gated CML high-speed bipolar circuits is presented. The analytical delay model accounts for different transistor sizes at the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML circuits. A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model

Keywords

bipolar logic circuits; circuit optimisation; current-mode logic; delays; equivalent circuits; logic design; transient analysis; analytical model; high-current effects; high-speed bipolar circuits; optimization; propagation delay time; series-gated CML bipolar circuits; two-level circuits; Analytical models; Circuit analysis computing; Circuit optimization; Circuit simulation; Circuits; Design optimization; Equations; Parasitic capacitance; Propagation delay; SPICE; Time sharing computer systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519010

Filename

519010