• DocumentCode
    275684
  • Title

    Mapping algorithms onto parallel architectures: time schedules

  • Author

    Shang, W. ; Fortes, J. A B

  • Author_Institution
    Southwestern Louisiana Univ., Lafayette, LA, USA
  • fYear
    1991
  • fDate
    15-19 Apr 1991
  • Firstpage
    65
  • Lastpage
    69
  • Abstract
    Time scheduling is one of the important problems faced in mapping algorithms onto parallel architectures, particularly in real-time fault-tolerant computing. The paper shows how linear schedules can be used to exploit parallelism available in nested-loop programs. It relates linear schedules to known loop transformation techniques for modeling the parallel execution and extracting parallelism of nested loop structures. These techniques are the Doaccross technique used to model the simultaneous execution of loop computations that belong to different iterations and a technique for parallelism exploitation called selective cycle shrinking. It is shown how selective shrinking is related to linear scheduling of nested loops and how to find the selective shrinking with minimum total execution time by applying techniques of finding optimal linear schedules. The execution of these schedules can be modeled using the Doaccross technique
  • Keywords
    fault tolerant computing; parallel algorithms; parallel architectures; parallel programming; real-time systems; scheduling; Doaccross; linear schedules; linear scheduling; loop transformation techniques; nested loop structures; nested loops; nested-loop programs; parallel architectures; parallel execution; parallelism; real-time fault-tolerant computing; selective cycle shrinking; selective shrinking; time schedules;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Design and Application of Parallel Digital Processors, 1991., Second International Specialist Seminar on the
  • Conference_Location
    Lisbon
  • Print_ISBN
    0-85296-519-2
  • Type

    conf

  • Filename
    140020