Parametric built-in self-test of VLSI systems

Author

Niggemeyer, D. ; Rüffer, M.

Author_Institution

Lab. for Inf. Technol., Hannover Univ., Germany

fYear

1999

fDate

9-12 March 1999

Firstpage

376

Lastpage

380

Abstract

Conventionally, Automatic Test Equipment (ATE) has been used for parametric tests of VLSI systems to determine the influence of clock speed, supply voltage, and temperature on the specified functionality of the circuit under test. This method is likely to become infeasible in the near future due to an aggressive drive to increased Overall Timing Accuracy (OTA), as predicted in the SIA Roadmap. In this paper, a method for Parametric Built-in Self-Test using on-chip Phase-Locked Loops (PLLs) is presented which is capable of overcoming the timing accuracy problem. A PLL-based test circuitry to determine the maximum frequency is described. Design constraints of the PLL control system, such as stability and resolution, are discussed for a specific design using 0.35 /spl mu/m CMOS technology. The functionality of the self-test circuitry is demonstrated to be competitive with parametric ATE tests such as Global Search Track without the need for expensive test equipment.

Keywords

CMOS integrated circuits; VLSI; built-in self test; integrated circuit testing; phase locked loops; 0.35 micron; CMOS circuit; VLSI system; automatic test equipment; global search track; overall timing accuracy; parametric built-in self-test; phase locked loop; Accuracy; Automatic test equipment; Automatic testing; Built-in self-test; CMOS technology; Circuit testing; Phase locked loops; System testing; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich, Germany

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761149

Filename

761149