Title :
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Author :
Kitsos, Paris ; Sklavos, Nicolas ; Skodras, Athanassios N.
Author_Institution :
Comput. Sci., Hellenic Open Univ., Patras, Greece
Abstract :
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power consumption reduction from 1.2 to 8.7 times is achieved by means of the proposed techniques compared with the implementation without any low power issue.
Keywords :
cryptography; field programmable gate arrays; low-power electronics; pipeline arithmetic; power consumption; random-access storage; Luffa hash function; embedded RAM block; gate level technique; low power FPGA; pipeline technique; power consumption; word length 256 bit; Clocks; Field programmable gate arrays; Logic gates; Pipelines; Power demand; Random access memory; Registers; FPGA; Low power design; Luffa hash function; hardware implementation;
Conference_Titel :
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on
Conference_Location :
Lille
Print_ISBN :
978-1-4244-7839-2
DOI :
10.1109/DSD.2010.19
