Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application

Author

Kumar, Deepak ; Kumar, Pankaj ; Pattanaik, Manisha

Author_Institution

VLSI Design Lab., ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India

fYear

2010

fDate

1-3 Sept. 2010

Firstpage

404

Lastpage

407

Abstract

This paper provides a detailed performance analysis of low power and high speed Look up Table (LUT) by using a circuit technique. Proper sizing of all the sleep transistors are done in the LUT to achieve an optimum power -delay relationship so that it can be used for fast growing low power applications. Also, we have implemented a benchmark circuit (8 × 10) encoder in Virtex-4, 90nm FPGA. As compared to the traditional 4-input LUT design, proposed design saves 12.8% of average power in high speed mode and 56.7% in low power mode with a little compromise in its speed.

Keywords

field programmable gate arrays; logic design; low-power electronics; table lookup; 4-input LUT design; Virtex-4 90nm FPGA; look up table; low power application; optimum power-delay relationship; performance analysis; size 90 nm; sleep transistors; Benchmark testing; Delay; Field programmable gate arrays; MOS devices; Performance analysis; Table lookup; Transistors; Field programmable gate arrays (FPGA´s); Look-up table (LUT); Virtex-4; deepsubmicron; delay; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on

Conference_Location

Lille

Print_ISBN

978-1-4244-7839-2

Type

conf

DOI

10.1109/DSD.2010.72

Filename

5615577