Title :
Efficient techniques for modeling chip-level interconnect, substrate and package parasitics
Author :
Feldmann, Peter ; Kapur, Sharad ; Long, David E.
Author_Institution :
Bell Lab., Lucent Technol., USA
Abstract :
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper we discuss some recent novel schemes for extraction and reduced order modeling that help overcome this computational bottleneck
Keywords :
frequency-domain analysis; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; time-domain analysis; IC design; IC modelling; chip-level interconnect; computational bottleneck; frequency-domain analysis; package parasitics; reduced order modeling; substrate parasitics; time-domain analysis; Circuit simulation; Electromagnetic modeling; Finite difference methods; Integral equations; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit packaging; Radio frequency; Radiofrequency integrated circuits; Time domain analysis;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761158
