Title :
Efficient switching activity simulation under a real delay model using a bitparallel approach
Author :
Bühler, M. ; Papesch, M. ; Kapp, K. ; Baitinger, U.G.
Author_Institution :
ISE-IPVR, Stuttgart Univ., Germany
Abstract :
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits is presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results
Keywords :
circuit optimisation; circuit simulation; combinational circuits; delay estimation; discrete event simulation; integrated circuit modelling; logic simulation; low-power electronics; bitparallel approach; circuit optimisation; combinational circuits; delay model; event driven simulation; gate level switching activity estimator; low power electronics; switching activity simulation; Circuit simulation; Clocks; Computational modeling; Delay; Logic; Power dissipation; Runtime; Statistics; Switching circuits; Utility programs;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761166
