Title :
An on-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs
Author :
Ker, Ming-Dou ; Wu, Chung-Yu ; Jiang, Hsin-Chin ; Lee, Chung-Yuan ; Ko, Joe ; Hsue, Peter
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500 V and ±400 V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108 μm×242 μm including the latchup guard-ring of 10-μm width and a 90 μm×90 μm metal pad for wire bonding
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; integrated circuit technology; protection; 400 V; 6500 V; complementary SCR structures; human-body-mode; latchup guard-ring; machine-mode ESD stresses; onchip ESD protection circuit; submicron CMOS ICs; Bonding; CMOS process; CMOS technology; Circuits; Diodes; Electrostatic discharge; Protection; Stress; Thyristors; Variable structure systems; Voltage; Wire;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519013
