Title :
A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI
Author :
Chen, Y.G. ; Kuo, J.B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a 1.5 V BICMOS dynamic subtracter circuit for low-voltage BICMOS CPU VLSI. With an output load of 0.2 pf, the 1.5 V BiCMOS dynamic subtracter circuit shows a more than 2.98 times improvement in speed as compared to the CMOS static one
Keywords :
BiCMOS logic circuits; VLSI; digital arithmetic; microprocessor chips; 1.5 V; BiCMOS dynamic subtracter circuit; low-voltage CPU VLSI; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Central Processing Unit; Circuit testing; Logic devices; MOS devices; Niobium; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519014
