• DocumentCode
    2757588
  • Title

    A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI

  • Author

    Chen, Y.G. ; Kuo, J.B.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    2
  • fYear
    1994
  • fDate
    3-5 Aug 1994
  • Firstpage
    1149
  • Abstract
    This paper presents a 1.5 V BICMOS dynamic subtracter circuit for low-voltage BICMOS CPU VLSI. With an output load of 0.2 pf, the 1.5 V BiCMOS dynamic subtracter circuit shows a more than 2.98 times improvement in speed as compared to the CMOS static one
  • Keywords
    BiCMOS logic circuits; VLSI; digital arithmetic; microprocessor chips; 1.5 V; BiCMOS dynamic subtracter circuit; low-voltage CPU VLSI; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Central Processing Unit; Circuit testing; Logic devices; MOS devices; Niobium; Switches; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
  • Conference_Location
    Lafayette, LA
  • Print_ISBN
    0-7803-2428-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1994.519014
  • Filename
    519014
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2757588