DocumentCode
2757697
Title
Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts
Author
Toulouse, A. ; Bernard, D. ; Landrault, C. ; Nouet, P.
Author_Institution
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear
1999
fDate
9-12 March 1999
Firstpage
576
Lastpage
580
Abstract
This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.
Keywords
capacitance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit testing; 3D modelling; analytical formulations; deep submicron dense layouts; inter-layer capacitances; interconnect capacitance extraction; process characterization approach; Analytical models; Calibration; Capacitance; Capacitors; Data mining; Integrated circuit interconnections; LAN interconnection; Numerical simulation; Semiconductor device modeling; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location
Munich, Germany
Print_ISBN
0-7695-0078-1
Type
conf
DOI
10.1109/DATE.1999.761185
Filename
761185
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