DocumentCode :
2757926
Title :
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
Author :
Ye, Lun ; Chang, Foong-Charn ; Feldmann, Peter ; Nagaraj, N. ; Chadha, Rakesh ; Cano, Frank
Author_Institution :
Bell Labs., Murray Hill, NJ, USA
fYear :
1999
fDate :
1999
Firstpage :
658
Lastpage :
663
Abstract :
Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and design complexity. As parasitic coupling capacitances are a significant portion of total capacitance in deep-submicron designs, verification of both performance and functionality assumes greater importance. This paper describes techniques for the modeling and analysis of parasitic coupling effects for large VLSI designs. Analysis results from a controlled experimental setup are presented to show the need for accurate cell models. Results from application of these techniques on a lending edge Digital Signal Processor (DSP) design are presented. Accuracy comparison with detailed SPICE-level analysis is included
Keywords :
VLSI; capacitance; circuit analysis computing; crosstalk; digital integrated circuits; integrated circuit interconnections; integrated circuit modelling; timing; DSP design; cell models; chip-level verification; coupling capacitances; deep-submicron digital designs; digital signal processor design; interconnect parasitics; large VLSI designs; parasitic coupling effects; Circuit testing; Coupling circuits; Crosstalk; Degradation; Delay; Instruments; Integrated circuit interconnections; Logic; Parasitic capacitance; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
Type :
conf
DOI :
10.1109/DATE.1999.761199
Filename :
761199
Link To Document :
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