Title :
On programmable memory built-in self test architectures
Author :
Zarrineh, Kamran ; Upadhyaya, Shambhu J.
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Abstract :
The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more efficient and flexible than existing architectures. Test logic overhead of the proposed programmable versus nonprogrammable memory BIST architectures is evaluated. The proposed programmable memory BIST architectures could be used to test memories in different stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and flexibility while having less test logic overhead than the programmable PSM-based memory BIST architecture
Keywords :
built-in self test; finite state machines; integrated circuit testing; integrated memory circuits; memory architecture; programmable circuits; FSM-based memory; built-in self test architectures; extendibility; flexibility; microcode-based memory BIST; programmable memory; test logic overhead; Automatic testing; Built-in self-test; Circuit faults; Computer architecture; Costs; Fabrication; Hardware; Logic arrays; Logic testing; Memory architecture;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761207
