Abstract :
Presents the design of a synthesiser based on a single phase locked loop, and capable of output frequencies of over 2 GHz, aimed at the portable radio market. Experimental results are presented for a prototype unit demonstrating the success of techniques to reduce the levels of phase noise and sidebands. These techniques are outlined and the results are analysed in detail. A new circuit configuration for the PLL is shown which greatly improves the overall performance of the synthesiser
