New parallel multipliers based on low power adders

Two new parallel multiplier architectures are designed based on two new full adders. These two adders are based on a new algorithm and display low power dissipation and high speed. The compactness and regularity of conventional array multipliers are maintained. The partial products are generated more efficiently using lower number of transistors. The proposed two multipliers offer significant improved performance, in terms of speed and power dissipation, than standard array multipliers