Real time 3D rendering patch processing using an embedded SIMD computer architecture

Author

Mrochuk, Jeff S. ; Elliott, Duncan G.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.

fYear

2005

fDate

1-4 May 2005

Firstpage

743

Lastpage

746

Abstract

This paper demonstrates that three dimensional imaging operations can benefit from the parallel processing provided by a single instruction multiple data (SIMD) processing array. The SIMD array used for implementation is a processor in memory architecture created by Atsana Semiconductor. This design is used in Atsana´s J2210 media processor, which is used as the test platform for this project. The J2210 is a system on a chip containing an ARMtrade microprocessor and a SIMD array processor. The goal is to test this SIMD architecture for suitability as a hardware acceleration system for real time rendering of 3D scenes in an embedded platform. SIMD architectures take advantage of data parallelism, which is readily available in 3D rendering

Keywords

embedded systems; memory architecture; rendering (computer graphics); embedded SIMD computer architecture; hardware acceleration system; memory architecture; real time 3D rendering patch processing; single instruction multiple data processing array; three dimensional imaging operations; Computer architecture; Embedded system; Energy consumption; Graphics; Hardware; Layout; Microprocessors; Parallel processing; Power system analysis computing; Rendering (computer graphics);

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2005. Canadian Conference on

Conference_Location

Saskatoon, Sask.

ISSN

0840-7789

Print_ISBN

0-7803-8885-2

Type

conf

DOI

10.1109/CCECE.2005.1557036

Filename

1557036