FGTMR - Fine grain redundancy method for reconfigurable architectures under high failure rates

For each new device generation based on smaller structures Single Event Errors (SEE) and intrinsic device faults gain more and more importance as device sensitivity increases. Triple Modular Redundancy (TMR) is a common reliability methodology for mitigating upsets and failures in architectures like modern Field Programmable Gate Arrays (FPGA). However for new device generations simply replicating complete systems may not be sufficient anymore especially in harsh environments, such as space applications, as higher failure rates may disturb a second instance before the faulty first one recovers. In this paper we focus on the Single Event Upset (SEU) mitigation challenges in nano scale architectures which can result in crucial situations. Our approach transforms the classical idea of TMR on module level down to a technological view based on FPGA architecture primitives. Such a fine grain approach allows to cope with several of the challenges caused by shrinking devices. This way the design can especially recover from multiple failures including Multiple Bit Upsets (MBUs). Moreover, we show how our approach can be integrated into standard tool flows thereby introducing TMR automatically. Finally we extend our idea to MBU tolerance by experiments.