Fixed-Point Implementation of Noise Reduction Using StarCore- SC3400

The presence of relatively high-level background noise in a telecommunication channel may lower the perceived voice quality of speech signals as well as degrade in-band signaling. The challenge is to reduce the noise to a satisfactory level while minimizing the use of computational resources. This paper describes an efficient noise reduction algorithm and its implementation on a high-performance digital signal processor (DSP) based on the freescale StarCoretrade SC3400 core. The NR implementation methodology takes advantage of the StarCoretrade architecture and Code Warriortrade development tools to reduce engineering efforts. After performing code optimization by exploring a mix of high-level and machine-level languages, the NR computational cost is reduced to approximately 0.6 millions of cycles per second for the narrow-band applications (i.e., G.711 with 8 kHz sampling rate). The algorithm has been evaluated using different approaches, including subjective evaluation by expert listeners. An overall noise reduction of 10-12 dB (for standard setting of 13 dB noise reduction threshold) has been achieved for most natural-speech signals polluted with stationary noise. The noise reduction component has also been evaluated using wideband signals (16 kHz sampling rate). The machine cycle count increased to 1 MCSP (approximately) while the overall noise reduction of 9-12 dB was achieved without observing adverse side effects related to voice quality.