• DocumentCode
    2760036
  • Title

    Timing yield slack for statistical optimization

  • Author

    Hwang, Eun Ju ; Kim, Wook ; Kim, Young Hwan

  • Author_Institution
    Pohang Univ. of Sci. & Technol., Pohang, South Korea
  • fYear
    2011
  • fDate
    19-20 July 2011
  • Firstpage
    125
  • Lastpage
    133
  • Abstract
    In deterministic timing optimization, timing slack is used to verify whether a timing violation occurs or not without timing updates on the entire circuit. However, in statistical timing optimization, there is currently no criterion to verify whether a timing violation occurs. This paper proposes a novel metric of timing yield slack to verify whether the timing yield violation occurs without updating the timing yield of the entire circuit. This paper also presents an efficient method to compute the proposed timing yield slacks of gates and a strategy to use timing resources for effective statistical optimization. Experimental results on ISCAS-85 benchmark circuits showed that the proposed timing yield slack calculation method has only a 1.89% error on average, and improves the runtime by 460 times as compared with the exact calculation method. Also, the proposed method has a small runtime overhead of 4.85% against the statistical static timing analysis.
  • Keywords
    circuit optimisation; integrated circuit yield; logic gates; ISCAS-85 benchmark circuit; deterministic timing optimization; gates; statistical timing optimization; timing violation; timing yield slack; timing yield violation; Complexity theory; Delay; Logic gates; Optimization; Probability; Process variation; statistical design; statistical optimization; statistical static timing analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4577-0145-0
  • Type

    conf

  • DOI
    10.1109/ASQED.2011.6111714
  • Filename
    6111714