Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Author

Jinho An ; Kwang-Jin Moon ; Soyoung Lee ; Do-Sun Lee ; Kiyoung Yun ; Byung-Lyul Park ; Ho-Jun Lee ; Jiwoong Sue ; Yeong-Lyeol Park ; Gilheyun Choi ; Ho-Kyu Kang ; Chilhee Chung

Author_Institution

Semicond. R & D Center, Samsung Electron. Co. Ltd., Hwasung, South Korea

fYear

2012

fDate

4-6 June 2012

Firstpage

1

Lastpage

3

Abstract

Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

Keywords

annealing; copper; electroplating; semiconductor device reliability; three-dimensional integrated circuits; 3D chip stacking technology; Cu; annealing process; electroplating chemistry; extrusion-type TSV; high performance mobile device; reliability; structural considerations; Annealing; Chemistry; Grain size; Microstructure; Process control; Stress; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2012 IEEE International

Conference_Location

San Jose, CA

ISSN

pending

Print_ISBN

978-1-4673-1138-0

Electronic_ISBN

pending

Type

conf

DOI

10.1109/IITC.2012.6251586

Filename

6251586