Uniform diameter and pitch co-design of 16nm n-type carbon nanotube channel arrays for VLSI

Author

Sun, Yanan ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2011

fDate

19-20 July 2011

Firstpage

211

Lastpage

216

Abstract

Uniform nanotube diameter and nanoarray pitch are essential for low-cost and high-yield manufacturability of billions of carbon nanotube MOSFETs (CN-MOSFETs) with various sizes on a single chip. In this paper, the optimum uniform diameter and pitch of 16 nm n-type CN-MOSFETs are determined with two different substrate bias voltages for a wide range of transistor sizes. A new quality metric is evaluated to identify the optimum device profiles suitable for very large scale integration.

Keywords

MOSFET; VLSI; carbon nanotubes; VLSI; carbon nanotube MOSFET; carbon nanotube channel arrays; high-yield manufacturability; low-cost manufacturability; n-type CN-MOSFET; nanoarray pitch; optimum device profiles; pitch co-design; quality metric; substrate bias voltages; uniform nanotube diameter; very large scale integration; Carbon nanotubes; Degradation; Electron tubes; Measurement; Substrates; Transistors; Very large scale integration; CN-MOSFET technology; Carbon nanotube very large scale integration (VLSI); charge screening effect; uniform nanoarray pitch; uniform nanotube diameter;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4577-0145-0

Type

conf

DOI

10.1109/ASQED.2011.6111747

Filename

6111747