Design of self-synchronized component FSMs for self-timed systems

Self-synchronized circuits are a design style that is very useful in practical controller design. There is little research on VLSI realization of low-power (pass transistor-based) and other asynchronous self-synchronized sequential circuits. The goal is to achieve fast circuits, with low power consumption, for deep sub-micron technologies. No specialized set of EDA (electronic design automation) tools or PLDs are now available that can be used for fast prototyping of such systems and FPGA components in them. This paper proposes a new design style for self-synchronized finite state machines (FSMs), demonstrates their usefulness by speed analysis, compares variants using a simple example, and proposes new types of EPLD (electrically programmable logic device)/FPGA chips to aid in the board-level design of self-synchronized circuits