Analysis, modeling and optimization of transmission gate delay

Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic dependency on chain-length. This necessitates buffer insertion at depth 3 or 4 for chain of transmission gate in the current analysis methodology. In this paper, the dependency on two more factors such as fan-out and input-pattern are discussed. We show that the delay is dynamic and exponential depending on input-pattern and fan-out respectively. As a consequence, the insertion of buffer at proper depth is necessary for different fan-out configuration. A restoring mode transmission gate (RMTG) XOR gate is proposed which shows little dependency on fan-out and input patterns thereby eliminate the complexity of buffer insertion. The Spice simulation in 180nM UMC Technology shows that our proposed RMTG XOR is 13.21% and 31.34% faster, 51.63% and 1.72% power efficient compared to the conventional CMOS XOR and TG XOR respectively for a load capacitance of 10 fF. Our proposed model consumes less hardware compared to the conventional CMOS XOR.