How to half the latency of IEEE compliant floating-point multiplication

Author

Seidel, Peter-Michael

Author_Institution

Dept. of Comput. Sci., Saarlandes Univ., Saarbrucken, Germany

Volume

1

fYear

1998

fDate

25-27 Aug 1998

Firstpage

329

Abstract

We present an IEEE compliant floating-point multiplier that computes the correctly rounded result for all representable floating-point values. This multiplier can be implemented in 2 clock cycles, whenever its adder tree fits in one clock cycle. For the same operation recent multiplier designs need at least 4 clock cycles including the pre and postprocessing for denormalized operands and multistep rounding for the support of different precisions. Our multiplier operates on an internal format that we introduce before. We discuss the changes that become necessary by the use of this format and the optimizations that are possible for the other arithmetic operations

Keywords

IEEE standards; adders; circuit optimisation; clocks; floating point arithmetic; multiplying circuits; IEEE compliant floating-point multiplication; adder tree; arithmetic operations; clock cycle; clock cycles; denormalized operands; floating-point multiplier; latency; multiplier designs; multistep rounding; optimization; Clocks; Computer science; Delay; Design optimization; Floating-point arithmetic; Graphics; Hardware; Microprocessors; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Euromicro Conference, 1998. Proceedings. 24th

Conference_Location

Vasteras

ISSN

1089-6503

Print_ISBN

0-8186-8646-4

Type

conf

DOI

10.1109/EURMIC.1998.711821

Filename

711821