Fault injection into VHDL models: analysis of the error syndrome of a microcomputer system

The paper presents the results of fault injection experiments to analyse the error syndrome of a microcomputer system. The faults have been injected at chip level in VHDL models, using an injection tool designed with this purpose. We have carried out a set of injection experiments. Transient faults has been injected (stuck-at and open line) on both the signals and variables of both processor and memory. We have classified and analysed the pathology of the errors and measured their latency. The results have shown that the majority of errors produced in the signals are of type Control Flow (46%), with a propagation latency of around half clock cycle. On the other hand, the prevailing errors in the model variables are of type Data (65%), with a propagation latency of about 2.5 clock cycles. These results can be used to focus the design of fault detection and fault tolerance mechanisms to increase the system dependability