A VLSI architecture of a DS-CDMA decision feedback multistage parallel interference cancellation detector

In direct-sequence code division multiple access (DS-CDMA) systems, performances are limited by multiple access interference (MAI). To mitigate this effect and hence provide a significant increase in capacity and allow high data rates, multiuser detection (MUD) techniques are used. The main drawback of such receivers is the increase in complexity when compared to the conventional receiver based on the Rake receiver. The multistage parallel interference cancellation (MPIC) receiver is considered a serious candidate for practical implementation showing a good tradeoff between performance and complexity. However, in order to satisfy the performances of the third generation systems, it is important to use MPIC with decision feedback (DF). The parallel implementation of the DF-MPIC is no longer straightforward. Hence, a new pipeline architecture of the DF-MPIC is proposed in this paper