How to address metallization and reliability challenges in today and tomorrows technology nodes?

Author

Preusse, Axel ; Hahn, Jens ; Chowdhury, Tamjid ; Hintze, Bernd ; Liske, Romy ; Nopper, Markus ; Stoeckgen, Uwe

fYear

2012

fDate

4-6 June 2012

Firstpage

1

Lastpage

1

Abstract

While dual damascene integration for current technologies is often cited for its challenges in regard to patterning and demands on lithography hardand software. Metallization for features with aspect ratios in the range of 4:1 as well as line widths with 40nm and shrinking is thought to be manageable with established technologies. Void free fill of lines and vias is mandatory yet reliability and line resistance gaining importance from one technology node to the next. Methods to enhance reliability are abound however which of the solutions are extendible to future technology nodes depends on a variety of parameters. The before mentioned topics on metallization challenges as well as choices to enhance reliability will be discussed in the paper.

Keywords

metallisation; semiconductor device reliability; current technology; dual damascene integration; line resistance; metallization; reliability; size 40 nm; Damascene integration; Lithography; Metallization; Resistance; Software; Software reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2012 IEEE International

Conference_Location

San Jose, CA

ISSN

pending

Print_ISBN

978-1-4673-1138-0

Electronic_ISBN

pending

Type

conf

DOI

10.1109/IITC.2012.6251655

Filename

6251655