Title :
Testing for tunneling opens
Author :
Li, James C M ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or IDDQ testing. Theoretical calculations as well as Boolean and IDDQ experiments confirm the existence of tunneling opens. The Murphy experimental data show that seven out of nine VLV-only failure circuits can be explained by this failure mode. All these seven circuits survived 366 hours temperature burn-in. Finally, a cost effective screening strategy is proposed
Keywords :
Boolean functions; CMOS memory circuits; combinational circuits; integrated circuit testing; logic testing; tunnelling; IDDQ testing; Murphy chips; at-speed Boolean tests; combinational circuits; cost effective screening strategy; digital CMOS test chip; temperature burn-in; tunneling-open failure mode; very LV testing; Acceleration; Circuit testing; Costs; Delay; Hot carrier effects; Leakage current; Low voltage; Temperature; Threshold voltage; Tunneling;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894195
