DocumentCode :
2761927
Title :
Application of deterministic logic BIST on industrial circuits
Author :
Kiefer, Gundolf ; Vranken, Harald ; Marinissen, Erik Jan ; Wunderlich, Hans-Joachim
Author_Institution :
Comput. Archit. Lab., Stuttgart Univ., Germany
fYear :
2000
fDate :
2000
Firstpage :
105
Lastpage :
114
Abstract :
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; integrated circuit testing; logic testing; ATPG; BIST hardware cost; IC testing; STUMPS; complete fault coverage; complete fault efficiency; deterministic logic BIST; industrial circuits application; scan-based BIST; sequence-generating logic; silicon area; test quality; test time; Built-in self-test; Circuit faults; Circuit testing; Clocks; Frequency; Integrated circuit testing; Logic circuits; Logic testing; System testing; Test equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
ISSN :
1089-3539
Print_ISBN :
0-7803-6546-1
Type :
conf
DOI :
10.1109/TEST.2000.894197
Filename :
894197
Link To Document :
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