Test structure verification of logical BIST: problems and solutions

Author

Cogswell, Michael ; Pearl, Don ; Sage, James ; Troidl, Alan

Author_Institution

Test Design Autom., IBM Corp., Endicott, NY, USA

fYear

2000

fDate

2000

Firstpage

123

Lastpage

130

Abstract

Test Structure Verification (TSV) is the process used to assess the conformance of a circuit to a set of predefine Design For Testability (DFT) rules. Test generation algorithms are typically optimized for circuits that are highly testable, so Test Structure Verification (TSV) ultimately indicates the overall testability of a circuit. Logical BIST (Built In Self Test) is a methodology based on signature analysis which produces patterns used to identify the correctness of the manufactured circuit via specially designed BIST hardware. This paper describes a set of proven production level procedures used to identify and verify the test structure and behavior of BIST hardware. These algorithms are based on the TSV implementation of IBM´s TestBench test generation system

Keywords

built-in self test; design for testability; logic testing; design for testability; logic circuit; logical built-in-self-test; signature analysis; test generation algorithm; test structure verification; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Hardware; Logic testing; Manufacturing; Pattern analysis; System testing; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894199

Filename

894199