DocumentCode :
2761979
Title :
DFT advances in Motorola´s Next-Generation 74xx PowerPCTM microprocessor
Author :
Raina, Rajesh ; Bailey, Robert ; Belete, Dawit ; Khosa, Vikram ; Molyneaux, Robert ; Prado, Javier ; Rasdan, A.
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
fYear :
2000
fDate :
2000
Firstpage :
131
Lastpage :
140
Abstract :
This paper shares techniques used to overcome DFT challenges on Motorola´s Next-Generation 74xx PowerPCTM microprocessor-a 700+ MHz microprocessor with an on-chip, 256 K byte second-level cache
Keywords :
cache storage; design for testability; integrated circuit testing; microprocessor chips; 256 Kbit; 700 MHz; DFT; Motorola Next-Generation 74xx PowerPC microprocessor; on-chip second-level cache; Built-in self-test; CMOS process; Copper; Cost function; Design for testability; Frequency; Logic design; Logic testing; Microprocessors; Signal design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
ISSN :
1089-3539
Print_ISBN :
0-7803-6546-1
Type :
conf
DOI :
10.1109/TEST.2000.894200
Filename :
894200
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2761979
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