Title :
The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core
Author :
McLaurin, Teresa L. ; Frederick, Frank
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
The DFT and Test challenges faced, and the solutions applied, to the newest member of the ColdFire(R) microprocessor family, the MCF5407, are described in this paper. The MCF5407 is the first member of the family to utilize a PLL-sourced clock to do at-speed launch-to-capture cycles. This PLL-sourced test clock can be “chopped” in any manner needed for core to asic ratios between 4:1 and 1:1. The internal microprocessor core of the MCF5407 was designed as a separate stand-alone core. The DFT challenges and solutions described in this paper involve the challenges that are above and beyond the challenges of the MCF5307; including the PLL clock chop and enhanced PLL scan testing
Keywords :
design for testability; digital phase locked loops; integrated circuit testing; microprocessor chips; ColdFire microprocessor; DFT; MCF5407; PLL clock chop; PLL scan testing; at-speed launch-to-capture cycle; fourth generation technology; testability; AC generators; Automatic test pattern generation; Automatic testing; Clocks; Cost function; Delay; Logic; Microprocessors; Phase locked loops; Signal generators;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894202
