Title :
Variance reduction using wafer patterns in IddQ data
Author :
Daasch, W. Robert ; McNames, James ; Bockelman, D. ; Cota, K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., OR
Abstract :
The subject of this paper is IddQ testing for deep sub-micron CMOS technologies. The key concept introduced is the need to reduce the variance of good and faulty IddQ distributions. Other IddQ based techniques are reviewed within the context of variance reduction. Using the SEMATECH data and production data, variance reduction techniques are demonstrated. The main contribution of the paper is the systematic use of the die location and patterns in the IddQ data to reduce variance. Variance reduction is completed before any IddQ threshold limits are set
Keywords :
CMOS integrated circuits; automatic testing; electric current measurement; fault diagnosis; integrated circuit testing; probability; production testing; ATE; IddQ data; NNR; SEMATECH data; deep sub-micron CMOS technologies; die location; faulty distribution; production data; test floor implementation; variance reduction; wafer patterns; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Design engineering; Integrated circuit testing; Laboratories; Large scale integration; Leakage current; Logic testing; Production;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894206
